The challenges facing the electronics design community today are significant. Advances in semiconductor technology have increased the speed and complexity of designs in tandem with growing time-to-market pressures. Electronic design automation (EDA) tools have evolved to handle the increasingly complicated task of designing, laying out, and verifying integrated circuit (IC) semiconductor devices (“chips”). In EDA, computers are extensively used to automate the design, layout and verification process. However, improvements in efficiency and quality are still desired.
In integrated circuit design, the logic function of a chip is modeled and simulated in register transfer level (RTL) languages such as “Very High Speed Integrated Circuit Hardware Description Language” (VHDL) or Verilog. Then, a “netlist,” that is, a description of the connectivity of an electronic circuit is generated by a compiler using a standard-cell library. A standard cell is a group of transistors and interconnect structures that provides a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverters, etc.) or a storage function (e.g., flipflop, latch, etc.). Based on the netlist, the physical layout of a chip is then generated by mapping RTL descriptions into an actual geometric representation of all electronics devices (e.g., logic gates, capacitors, transistors, etc.) that will be implemented on the chip.
Traditional IC design flow clearly separated the logical front-end flow from the physical back-end flow. Physical back-end flow involves application-specific integrated circuit (ASIC) partition to several blocks and top level design which interconnects these blocks. The partitioning is desirable in order to facilitate hierarchical distributed ASIC implementation. Top level design and block partitioning may be implemented in parallel using separate resources and be limited to a physical size that can be handled by automatic EDA tools in terms of CPU run time and memory requirement.
With no block level physical view of the design, conventional top level full-chip physical implementation was based on timing calculations from relatively basic estimates of interconnections between portions of the design. This often resulted in multiple physical implementation iterations for timing closure, that is, a process of modifying the design to meet the timing requirements. Such iterations may cause inefficiency in backend flow that may delay the scheduled manufacture time. Furthermore, the lack of ability to utilize static timing analysis (STA) during top level implementation process, that is, a method of computing the expected timing of a digital circuit based on advanced electricity algorithms, may result in a lower quality design. Therefore, improvements to increase design efficiency and quality is desired.
Specifically, there are two problems that the IC design industry is facing: inefficiency and low quality. In ASIC design, the bottom-up backend design flow makes the design flow inefficient. And, there are many top to block level iterations for timing closure, resulting in tape out schedule bottlenecks. This often leads to inefficiency. Furthermore, manual and script based timing-blind top level implementation flow without STA algorithms and optimization abilities utilization may result in overdesign and low product quality, meaning suffering from penalty in terms of optimizing area, power, or yield. Therefore, improvements to increase design efficiency and quality is desired.